1. Field of the Invention
The present invention relates to a device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor, and more particularly, to a device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.
2. Description of the Related Art
An electronically programmable output impedance circuit is described in U.S. Pat. No. 5,708,379, issued Jan. 13, 1998 to Yosinski. The electronically programmable output impedance circuit therein is employed in a very specific manner in an AC source/analyzer product family, but has broader application.
The AC source/analyzer product family includes models which are DC-coupled and which also employ a novel feedback circuit, an output impedance circuit, which is described in U.S. Pat. No. 5,708,379 issued to Yosinski, which causes the source part of the product to exhibit a controlled non-zero output impedance. The output impedance may be set to be resistive or inductive. It may also be set to a complex value that is equivalent to series-connective resistive and inductive components. The magnitudes of the resistive and inductive components are programmable. For realizations in the AC source/analyzer products, the resistive component may be set to values between zero and one ohm, and the inductive component to values between 20 uH and 1 mH. Different ranges are possible subject to constraints imposed by necessity of maintaining stability in feedback loops.
DC-coupled members of the AC source/analyzer product family also employ another feedback circuit, a DC offset elimination circuit used as a DC servo control loop that may be enabled to eliminate unwanted DC offset voltages at the product's output.
As will be shown below, the output impedance circuit and the DC offset elimination circuit, when active simultaneously, interact in an undesired manner that compromises the functionality and performance of the output impedance circuit at low frequencies including DC.
Practical applications for DC-coupled laboratory grade AC sources require simultaneous operation of both the output impedance circuit and the DC offset elimination circuit mentioned above. When AC sources are used to simulate AC power systems, it is desirable to have both resistive and inductive source impedances, since real systems exhibit a finite source impedance which includes both components. The magnitudes of the impedance components vary widely in real systems, making programmability highly desirable.
Aside from the effects of source impedance, actual AC power systems appear as nearly ideal sources for loads of the size that may powered by all but the very largest laboratory grade AC sources. To the extent that the source acts ideally, it will be capable of supplying any amount of current at any frequency. For this reason, it is essential for the output impedance circuit to work properly at very low frequencies including DC. Loads with varying current consumption, for example, may exhibit “beat-frequency” effects that produce AC power system currents at low frequencies and/or DC. Adjustable speed drives (ASDs) are a commonly encountered example of such loads. Another common example is a half-wave rectified load which draws DC current from an AC power system.
Aside from the desired property of correctly simulating effects of source impedance and DC load current, it is otherwise essential to have as little DC voltage present at the output of laboratory grade sources as possible since equipment with line-connected power transformers may exhibit very little tolerance for DC voltage. DC levels of just a few millivolts can cause power transformers in the supplied equipment to saturate.
On the other hand, it is undesirable for the source to actually be AC-coupled using, for example, an output transformer since practically-sized output transformers exhibit properties that preclude proper simulation of many events with DC content that occur in AC power systems. Examples include partial cycle dropouts, non-symmetrical voltage waveforms, etc.
To assist in an understanding of the present invention, it is helpful to understand the operation of the output impedance and DC offset elimination circuits. In the discussion that follows, operation of the circuits is considered independently and then in combination. Highly simplified circuits imported from a circuit simulator and scaled to nominal values will be used to develop an understanding of the essential concept of the present invention.
FIG. 1A shows a very basic voltage source 100 which includes an inverting power amplifier 102. A DC voltage source 104 is shown to represent an accumulated effect of undesired offset voltage sources encountered in practical devices. For the sake of simplicity, the overall gain to the output of the basic voltage source 100 is set to −1. A current sensing element, or shunt, identified as 106, is coupled to 1000× differential gain block 108 (hereinafter referred to as “differential gain block”) to provide a voltage output proportional to output current. Actual implementations may use differential amplifiers, but otherwise, the function and value for the current sensing element 106 and associated differential gain block 108 are as might be encountered in practice.
Feedback is provided through an operational amplifier 110 which is configured as a unity gain follower. The voltage at the output side of the current sensing element 106 is connected to the positive terminal of the operational amplifier 110. The feedback sensing point is selected to cause voltage drops across the current sensing element 106 to be inside of the feedback loop, so that the voltage at the right hand, or output, side of current sensing element 106 is regulated by the action of the feedback. A resistor 114 is connected between the output terminal of the operational amplifier 110 and the negative terminal of the inverting amplifier 102. A resistor 116 is connected between the DC voltage source 104 and the negative terminal of the differential amplifier 102. A circuit comprising power amplifier 102, operational amplifier 110, and associated input and feedback resistors 114, 116, and current sensing element 106 are thus configured to function as an ideal voltage source. As an example, current sensing element 106, and resistors 114 and 116 have the values 0.001 ohm, 10 k ohm and 10 k ohm, respectively.
Typically, another differential amplifier would be used in a voltage feedback signal path, but for purposes of this example, it is useful to include the operational amplifier (configured as a unity gain follower) 110 as shown since it is functionally transparent except for its action to prevent current flowing in the feedback resistor 114 from becoming part of the total current sensed by the current sensing element 106. Thus, only the load current is shown in meter 122. One volt displayed in meter 122 corresponds to one ampere of load current. All of the meters 120, 122, 124 shown in FIG. 1A are DC sensing.
A one-ampere current sink 118 is connected to the output node of the voltage source 100 in FIG. 1A. The resulting current flow develops a voltage across current sensing element 106 which is amplified by the associated differential gain block 108 and displayed as 1 volt in meter 122. As would be expected with an ideal voltage source, the load current produces a negligible voltage drop at the voltage source output as shown by meter 120.
FIG. 1B shows essentially the same circuit as shown in FIG. 1A, but with DC input voltage source 104 set to −1 volt to represent significant accumulated DC offset error voltage. In this case, an output voltage of +1 volt is now observed at meter 120, consistent with the operation of the overall circuit as a unity gain inverter. Since the current sink 118 representing the load remains set to one ampere, the change in output voltage produces no additional current flow.
FIG. 1C shows the same circuit as shown in FIG. 1B, but with the current sink 118 replaced by a resistor 132. In this example, the resistor 132 has a value of one ohm. Consequently, one ampere of load current flows, as a result of the +1V output produced by DC input voltage source 104 representing accumulated DC offset error voltages.
FIG. 1D shows the same circuit as shown in FIG. 1A with an additional resistor 134 placed between the current sink 118 and a feedback sensing point 136 at the right-hand side of the current sensing element 106. In this example, the resistor 134 has a value of one ohm. As in FIG. 1A, the DC input voltage source is set to 0.0V. Note that the output voltage shown by meter 120 is now −1 volt, reflecting the voltage drop across the resistor 134 induced by the load current. Note also that FIGS. 1A through 1D all show a voltage at the output terminal of inverting amplifier 102 which is 1 mV greater than the output voltage or, in the case of FIG. 1D, than the voltage at sensing point 136. The difference reflects the voltage drop developed in response to the flow of one ampere through the resistance of 0.001 ohms for current sensing element (shunt) 106 as given for purposes of example.
FIGS. 1A through 1D depict basic configurations of a source part of an AC source/analyzer product, and show how internal DC offset voltage errors are transferred to the output where they may produce undesired effects in a connected load. In addition, these figures help illustrate an important distinction between output currents that are “source-induced” as compared to output currents that are “load-induced.”
The current in FIG. 1C is source-induced in the sense that an output voltage is required to produce current flow in a connected load. The load in this case is represented by the resistor 132, but may be more generally represented by any complex impedance. In contrast, the current in FIGS. 1A, 1B and 1D is load-induced in the sense that the current flow is independent of the output voltage. More generally, this current may flow at any frequency including DC and, to the degree that the source/sink representing the load is ideal, the current flow is independent of and unaffected by changes in the source output voltage.
If the convention is adopted that current flow from the source into the load is considered “positive,” it may be observed from FIG. 1C that the output voltage producing the source-induced current has the same polarity as the current. On the other hand, if the source has a finite output impedance as represented by the resistor 134 placed outside the feedback loop in FIG. 1D, load-induced currents will cause an output voltage that is opposite in polarity from the current flow.
In FIG. 1B the current polarity and output voltage polarity are the same, but the output voltage is produced in response to DC input voltage source 104, not in response to load current. This may be seen by referring to FIG. 1A where DC voltage source 104 is set to 0.0V while current sink 108 remains set to 1 ampere, but in this case no output voltage results.
The significance of the distinction in polarities observed for source-induced and load-induced currents in the presence of output impedance will be described in detail with regard to the present invention.
FIG. 2 shows the basic voltage source 100 shown in FIG. 1B with a simplified representation of a DC offset elimination circuit 200 added thereto. The DC voltage source 104 has a value of −1 volt in this example. The DC offset elimination circuit 200 includes an operational amplifier 202 which is configured as a differential integrator having for practical purposes infinite gain at DC and unity gain at a frequency defined by a time constant for the RC elements comprising resistor 204, resistor 212 and capacitors 206 and 208. The values of the two resistors are normally set to be equal; the same being true also for the capacitors 206 and 208. The resistors 204 and 206 in this example have values of 100 k ohm and the capacitors 206 and 208 have values of 1 uF. For these values, unity gain occurs at 1.59 Hz.
Operational amplifier 202 and associated elements 204, 212, 206, and 208 together compromise the differential integrator. A resistor 212 is connected to the positive input of voltage follower 110 and to the right-hand side of current sensing element 106 (the output of the voltage source 100). With this connection for resistor 212, the differential integrator comprised of amplifier 202 and associated elements is configured to sample the output voltage (and DC content thereof) of voltage source 100.
A resistor 210 has an end connected to the output of the amplifier 202 (as well as an end of the capacitor 206). The resistor 210 has a value of 10 k ohm in this example. The other end of resistor 210 is connected to the junction of resistors 116, 114 and the negative input terminal of the inverting power amplifier 102. This connection to the “summing junction” of amplifier 102 provides means for the differential integrator to introduce corrective feedback to eliminate undesired DC voltages from the output of voltage source 100. As noted above, the conditions in FIG. 2 are as for FIG. 1B, that is, with DC input voltage source 104 simulating accumulated DC offset error voltages set to −1V. This condition should produce +1 volt at the output of voltage source 100, however, the action of the DC offset elimination circuit 200 serves to introduce corrective feedback via resistor 210 which removes DC voltage from the source's output that otherwise would be observed given the DC input source.
From a frequency response standpoint, the action of the DC offset elimination circuit 200 behaves as a first order high-pass function resulting in a diminishing effect at higher frequencies. The −3 db corner frequency is effected by both the ratio of the feedback resistor 210 to input resistor 116 and by the unity gain frequency of the differential integrator. When the resistor ratio is unity (as evidenced by both the resistor 210 and the resistor 116 having values of 10 k ohm in this instance), the integrator unity gain frequency equals the −3 db frequency for the overall system. At AC power system frequencies, the effect of the DC offset elimination circuit 200 is sufficiently small that the AC gain error for voltage source 100 is less than 0.02% for AC signals introduced at the location of voltage source 104 (the nominal input for voltage source 100).
For a product designer, the circuit shown in FIG. 2 imposes a design tradeoff that must be appropriately resolved for an intended application. If the corner frequency for DC offset elimination circuit 200 is set too high, unnecessarily large AC gain errors result at power system frequencies, thus compromising the source's function as an ideal AC power source. On the other hand, if the corner frequency is set too low, the DC offset elimination circuit 200 will fail to adequately remove undesired error voltages at near-DC frequencies. Generally, the corner frequency will be set as high as possible without unacceptably impacting gain accuracy at AC power system frequencies (e.g., at 50, 60 and 400 Hz).
This distinction in frequency between desired and undesired source-induced signals is critically relevant for the present invention as will be explained later.
FIG. 3 shows the basic voltage source 100 of FIG. 1B with an output impedance circuit 250. The output impedance circuit 250 includes a resistor 252 connected between the negative input terminal of power amplifier 102 and the output of the differential gain block 108. In this example, resistor 252 has a value of 10 k ohm. In this case, only a fixed resistive feedback loop is shown. Circuit values are scaled to cause output impedance, in this case resistance, of one ohm. In very simple terms, the circuit acts to generate a feedback signal to summing junction 254 (formed at the negative input terminal of power amplifier 102 by the junction of resistors 116, 114 and 252) that is proportional to output current. For the values indicated, one ampere of output current produces a one volt change in the output voltage thus corresponding to one ohm of resistive output impedance. The output voltage shown by meter 120 is entirely due to the flow of current through the output impedance since the DC error input voltage source is set to 0.0V. As shown previously in FIG. 1D, the output voltage is opposite in polarity from the output current according to the previously established convention that current flow from the source to the load represents positive current flow. Opposition in polarity occurs because, as also noted previously, the current flow is load induced in this example.
The operational amplifier 110 has infinite input impedance because it is an ideal component such that no current flows in that path.
The differential gain block 108 senses the voltage developed across current sensing element 106 in response to current, and develops an output voltage which is proportional to current, in this case, one volt is equal to one ampere. The voltage at the output of differential gain block 108, when directed as feedback through resistor 252 has the effect of creating an output impedance. This result occurs because the sign of the feedback is selected such that the overall feedback to summing junction 254 of inverting power amplifier 102 (including that provided via voltage follower 110 and resistor 114) reaches equilibrium when the output voltage has in fact dropped slightly in response to output current. The combined action of the two feedback paths (one via resistor 114 and the other via resistor 252) effectively creates the same behavior at the output of voltage source 100 as would be observed with actual source impedance.
FIG. 4A shows the basic voltage source 100 with both the DC offset elimination circuit 200 shown in FIG. 2 and the output impedance circuit 250 shown in FIG. 3 added thereto with a −1V DC input voltage as previously shown in FIG. 1B.
In FIG. 4A, the DC error input voltage 104 is set to −1V. The DC offset elimination circuit 200 correctly removes the effect of the DC error voltage from the source's output, but in addition acts to incorrectly remove the output voltage that should result from one ampere of load-induced current flowing through the one ohm output impedance synthesized by the action of feedback of a signal proportional to output current via resistor 252. The true nature of this undesired effect is more obvious when viewed in the frequency domain as shown in FIG. 4B. Substitution of a voltage controlled swept-frequency one ampere AC current sink 260 for the fixed one ampere DC current sink 118 (see FIG. 4A) as given in FIG. 4C permits the frequency response of the output impedance to be observed. Note that the meters shown in FIG. 4C are now AC responding.
FIG. 4B shows the voltage appearing at the output of voltage source 100 in response to the swept one ampere load-induced current produced by the voltage controlled AC current sink comprised of current sink 260 and the controlling voltage source 262. From FIG. 4B, it may be seen that the load-induced current approximately produces the expected one volt at the source's output for frequencies above 10 Hz, but if frequencies fall below 10 Hz, the expected output voltage is increasingly removed by the action of the DC offset elimination circuit 200. The effect is equivalent to reducing the output impedance as the frequency approaches DC. This result is contrary to the desired effect since a resistive output impedance should remain constant with respect to frequency. The −3 db point in the response is at 1.59 Hz due to the combined effect of the integrator time constant and the feedback ratio as described previously. The phase angle at frequencies well below the −3 db point reflects the fact that the impedance at those frequencies appears inductive rather than resistive as desired. This outcome would be expected from a magnitude response that increases by 20 db per decade with increasing frequency, but frequency dependency remains undesired.
One of the uses for the AC source product shown in FIG. 4A is to conduct tests of a wide range of electronic equipment for compliance with international standards for certain types of low frequency emissions that come from products, and in particular, one of these compliance tests is for a type of emission called flicker. Flicker is the varying light intensity observed when incandescent lamps are subjected to varying AC voltages induced by time-varying currents in AC power systems having source impedance.
Many people think of an AC power, or mains, system as an infinite source, in other words, as a voltage source with no source impedance. In fact, any mains system has a fairly significant amount of impedance. Accordingly, when conducting flicker tests it is necessary for the source to exhibit an output impedance similar to that encountered in actual mains systems. For any type of equipment connected to the AC power source, practical embodiments of AC source products such as shown in FIG. 4A attempt to simulate the source impedance of the main system when conducting flicker tests.
There is generally a standard or reference value which is specified in the emissions standard. For European 50 Hz ompliance test standards this value is 0.4+j0.25 ohm, that is, 0.4 ohms resistive and 796 uH of inductance. Different, but similar, values will typically be specified for AC mains systems in other regions of the world. Further, it may be desired to set the source impedance to a reference output impedance value for tests other than flicker compliance tests. This may be desired since similar values will be encountered in real mains systems and thus having these values present allows the AC source to better simulate the environment within which the equipment under test (EUT) actually will operate in practice.
Thus, AC source/analyzer products which are practical embodiments of the circuit shown in FIG. 4A seek to simulate source impedance with a feedback loop. However, as noted above, there is another loop which is directed towards removing a DC voltage from the output because an ideal main system has no DC content. Of course, a truly ideal mains system has no output impedance either, but as described above source impedance either is required for conducting certain compliance tests or may be desired for purposes of more accurately simulating actual mains system environments. The problem that occurs with embodiments such as given in FIG. 4A is that the DC offset elimination loop interferes with the output impedance loop as you approach DC, and in fact, it totally corrupts the same when you get to DC. Accordingly, there is no source impedance at DC, but such a situation is not desirable since it does not properly simulate the actual situation in mains systems. A pure inductance approaches zero impedance as the frequency approaches DC, but resistance is constant with frequency. As shown in FIG. 4B, the interaction between the impedance loop and the DC offset removal loop is such that the entire output impedance including the resistive component improperly approaches zero impedance as the frequency approaches DC. For the circuit values given as an example in FIGS. 4B and 4C, significant errors begin to be introduced about 10 Hz.
One presumption is that if all else fails, output impedance may be implemented by actually putting a discrete inductor and resistor in series with the output of a product; in other words, by using physical components. If one does that, there is no problem with whether the source works properly at DC. There are other problems, however. First, the resistive component dissipates a significant amount of power leading to inefficient operation and possible design tradeoffs. Secondly, since it is desired to have a range of values available for both the resistive and inductive components, advantages of cost-effective programmability attendant to a loop implemented approach as given in FIG. 4A are lost. It is possible to construct a programmable discrete component based series impedance, however, such implementations will be large, costly, and most likely unable to effectively simulate low impedance. This last problem occurs because parasitic resistance of switching elements such as relays will be significant and variable with time therefore difficult to characterize and control yet these same switching components are necessary to implement programmability.
As noted above, it is desired that the resistive component of the output impedance remain constant with frequency including DC. Further, it is desired also that the inductive component should be an impedance which is controlled solely by the selected inductance value and frequency and which is not influenced in addition by interaction with the DC offset removal loop. The reason why this behavior matters is that if there is an equipment connected as a test load which has a varying current, the current is effectively amplitude modulated. Amplitude modulation produces energy at side band frequencies about the carrier which in this case is the line frequency. These side bands can go down to DC for certain types of equipment, so for purposes of characterizing load-induced voltage drops across the AC system impedance it is quite relevant as to whether or not you have the proper impedance at DC.
One possible way to solve such a deficiency is by turning off the loop that removes the DC, but then DC voltages would be present which is also undesired.
The above-described power source circuit is an AC source which is DC capable. It is a switch mode inverter which provides an AC output at relatively high power and simulates the AC power, or mains, system as a source, but is DC coupled.
The AC mains system is inherently AC coupled. There are transformers all throughout the system and at multiple levels between low power loads that are plugged into a conventional wall outlet and the system generator or source. Despite the fact that the system is not an ideal source for most low power equipment, the system looks like it is a very large source compared to the power that the load is drawing. Because the system is large compared to low power loads, it can support DC current drain from products without an apparent generation of DC voltage. Connected loads drawing DC current induce DC voltages in the source because of the source impedance, but this situation is quite different from subjecting the load to a source-induced DC voltage. The reason for this primarily has to do with transformers and the products themselves. If the product itself includes a power transformer and it's a relatively high powered product, on the order of a kilowatt or so, a few millivolts or a few tens of millivolts of DC can cause the product's power transformer to saturate. Saturation produces abnormal operation in the load and for this reason it is very undesirable to have uncontrolled DC present in the source. Smaller products may be less susceptible to saturation in the presence of a particular level of DC source voltage, but the risk of transformer saturation remains.
One of the problems with the situation described is that there is no way to know what the load is. It may be large or small and it may or may not include a power transformer. The AC power source product is intended to be general purpose and therefore capable of acting as a power source for virtually any type of load. Thus, there is a situation where some loads will be susceptible to the problems with DC content, and some won't, but there is no way of knowing, which basically creates a situation where it is necessary to minimize source induced DC content. The problem is that the most effective way to do this because of practical constraints is to put a DC offset voltage elimination loop in the system. Consideration was made of improving the quality of the components and the products themselves so as to eliminate the need for the DC offset elimination circuit loop or not use it when tests are being conducted where the output impedance presence is desired. However, such a modification would add a significant amount of cost and not improve the results to a satisfactory level. Certainly, the benefit would not be to the degree that would be achieved by keeping the DC offset removal loop operational.
If both the DC offset elimination circuit and the output impedance circuit are operating at the same time, the DC offset elimination circuit is incapable of distinguishing between low frequency AC and/or DC voltages appearing at the source output that are caused by the source as opposed to ones that are caused by the load. It is acceptable to have voltages developed at the output that are caused by load behavior, but one does not want DC voltages at the output caused by source behavior.